System Diagram

Figure 1. High-Level System Block Diagram
Note:
  1. Proper decoupling capacitors are recommended to be placed close to the power pins of the module.
  2. VIO1 and VIO2 should be set to 3.3V or 1.8V depending on the system voltage. VIO2 can only be set to 1.8V if PSRAM variants are used.
  3. Pull-up resistor, e.g. 100K ohm, is required to be placed to nRESET line.
  4. LOGGER and GPIO37 are sensed by the device during boot, with boot value to be "10", which is LOGGER pin being pulled up and GPIO37 pin being pulled down.
  5. SWDIO and SWCLK is for SWD debug, recommended to be exposed to the test points or headers.
  6. LOGGER is for logs output, recommended to be exposed to a test point or hearer.
  7. COEX I/F is the coexistence interface.
  8. For PCB trace antenna variants, the external antenna and its matching circuit are not needed.
  9. For U.FL varants, the antenna is connected through U.FL connector.